Nonvolatile memory devices such as flash memories are commonly used as mass data storage subsystems. Such nonvolatile memory devices are typically packaged in an enclosed card that is removably connected with a host system, and can also be packaged as the non-removable embedded storage within a host system. In a typical implementation, the subsystem includes one or more flash devices and often a subsystem controller.
Current commercial memory card formats include that of the Personal Computer Memory Card International Association (PCMCIA), CompactFlash (CF), MultiMediaCard (MMC), Secure Digital (SD), MemoryStick, and MemoryStick-Pro. One supplier of these cards is SanDisk Corporation, assignee of this application. Host systems with which such cards are used include digital cameras, cellular phones, personal computers, notebook computers, hand held computing devices, audio reproducing devices, and the like.
The nonvolatile memory devices themselves are composed of one or more arrays of nonvolatile storage elements. Each storage element is capable of storing one or more bits of data. One important characteristic of the nonvolatile memory array is that it retains the data programmed therein, even when power is no longer applied to the memory array. In contrast, a volatile memory device requires that the power to the array be refreshed periodically in order to preserve the data contained in the volatile memory array. Another characteristic of nonvolatile memory is that once a cell contained within a nonvolatile memory array is programmed, that cell must be erased before it can be reprogrammed with a new data value.
The physical means for storing the charge in the memory cell can be implemented by using a floating gate transistor, such as an electrically erasable programmable read only memory (EEPROM). One known problem with floating gate devices such as EEPROMs is that the floating gate eventually wears out and breaks down after a very large number of write, program and erase cycles. When this happens, the cell is no longer usable and must be taken out of the list of available memory cells in the array. This sort of defect is called a “grown” defect. In one commercially available implementation, these defects are dealt with by mapping out the defective cells and substituting the physical addresses of good memory cells for the newly detected defective memory cells. Examples of implementations where defective cells or sectors are mapped out and replaced are described in U.S. Pat. No. 5,659,550 issued on Aug. 19, 1997 by Mehrotra et al.; U.S. Pat. No. 5,671,229 issued on Sep. 23, 1997 by Harari et al.; and in U.S. Pat. No. 5,862,080 issued on Jan. 19, 1999 by Harari et al., which applications are expressly incorporated herein in their entirety by this reference.
Arrays of nonvolatile memory cells typically are partitioned into groups to provide for efficient implementation of read, program and erase functions. For example, in many nonvolatile memory architectures, the memory cells are arranged into a larger group called a unit of erase. This unit of erase is the smallest number of memory cells that are erasable at one time.
The size of the unit of erase depends on the memory architecture that is being implemented. In earlier nonvolatile memories, the unit of erase was a block that was the same size as a standard 512-byte disk drive sector. In one commercial form, each block contained enough cells to store one sector of user data plus some overhead data related to the user data and/or to the block in which it was stored. In order to ensure that the blocks of cells were individually erasable, the blocks had to be sufficiently isolated from one another.
Because this isolation took up valuable space on the integrated circuit chip, another memory architecture was developed in which the unit of erase was made significantly larger so there would be less space required for such isolation. An example of this large block system architecture is described in U.S. Pat. No. 6,580,638 issued on Jun. 17, 2003 by Conley et al., which is a continuation of U.S. Pat. No. 6,426,893 issued on Jul. 30, 2002. Both of these patents are expressly incorporated herein in their entirety by this reference. In a large block system, the unit of erase is often further partitioned into individually addressable pages that are the basic unit for reading and programming user data (unit of programming and/or reading). In one commercial implementation, the unit of erase is a metablock. A metablock is a virtual unit of erase that is composed of multiple physical units of erase. These multiple physical units of erase can be used in parallel program and erase operations, but are addressed as a single logical block.
One method of forming metablocks, or “super” blocks is described in U.S. Pat. No. 6,034,897, which is expressly incorporated herein in its entirety by this reference. As described therein, for a memory having a number of devices, the same physical block in each of the devices is grouped into a metablock. Although this allows for the formation of metablocks and all of the blocks in a given metablock to be addressed by the same address, namely the address of the block in the first of the devices, it has a number of limitations. For example, as the linking of blocks into metablocks is pre-determined in this fixed configuration, when a block goes bad, the metablock to which it belongs becomes bad despite the other blocks within it still being functional. Thus, it is desirable goal to provide a system and method for an adaptable metablock arrangement without the operational overhead of establishing a new linking every time one is needed.